Session 1: Integration | |
| Applications & 3D Technology | P. Marchal, IMEC |
| Synergistic Combinations of Dielectrics and
Metallization Process Technology to Achieve
22nm Interconnect Performance Targets | G.A. Antonelli, Novellus |
| Competitive and Cost Effective Copper/Low-k
Interconnect (BEOL) for 28nm CMOS Technologies | R. Augur, GlobalFoundries |
| Effective Cu Surface Pre-treatment for High-reliable 22nm node Cu Dual Damascene Interconnects with High Plasma
Resistant Ultra Low-k Dielectric (k=2.2) | F. Ito, Renesas |
| Low k (k=3.0)/Cu Dual Damascene Process for Sub-40nm DRAM | S. D. Nam, Samsung |
| Effects of Cu Surface Roughness on TDDB for Direct Polishing Ultra-Low K Dielectric
Cu Interconnects at 40nm Technology Node and Beyond | W.C. Lin, UMC |
| Internal Repair for Plasma Damaged Low-k Films by Methylating Chemical Vapor | S. Nagano, Taiyo-Nippon Sanso Corporation |
| Influence Of Porosity On Electrical Properties Of Low-K Dielectrics | E. Van Besien, IMEC |
| Influence of Thermal Cycles on the Silylation Process For Recovering K-Value and Chemical Structure of Plasma Damaged Ultra-Low-K Materials | T. Fischer, TU Chemnitz |
Session 2: Reliability & Packaging | |
| Mechanical Reliability Outlook of Ultra Low-K Dielectrics | X.H. Liu, IBM |
| Evolution of Stress Gradients in Cu Films and Features Induced by Capping Layers | C. Murray, IBM |
| Copper Microstructure: EM Void Dynamics | C. Witt, GlobalFoundries |
| Plastic Relaxation during Thermal Loading in Advanced Cu Interconnects at Intermediate Temperatures | A.S. Budiman, CINT LANL |
| Modeling of dielectric reliability in copper damascene interconnect systems under BTS conditions | P. Belský, TU Chemnitz |
| Processing and Moisture Effects on TDDB for Cu/ULK BEOL Structures | E. Liniger, IBM |
| Electromigration Performance of Lead-Free Solder Balls for Surface-Mount Packaging Applications | C. Hau-Riege, Qualcomm |
Session 3: 3D | |
| CMP Process Development for the Via- Middle 3D TSV Applications at 28nm Technology Node | T. C. Tsai, UMC |
| A Robust TSV Middle Scheme for 3D Interconnects Technology | K. Moon, Samsung |
| Stress and Diffusion Resistance of Low Temperature CVD Dielectrics for Multi-TSVs on Bump-less Wafer-on- Wafer (WOW) Technology | H. Kitada, University of Tokyo |
| Characterization of Local Strain around Through-Silicon Via Interconnects by using X-ray Microdiffraction | O. Nakatsuka, Nagoya University |
Session 4: Metallization | |
| Metallization Opportunities and Challenges for Future Back-End-of-the-Line Technology | C. Cabral, Jr., IBM |
| Co Capping Layers for Cu/Low-k Interconnects | C. C. Yang, IBM |
| Metallization Options for Sub-30 nm Interconnects: Comparison of Cu and W Metallizations | L. Carbonell, IMEC |
| Ultimate Limits of Conventional Barriers and Liners-Implications for the Extendibility of Copper Metallization | E. Eisenbraun, CNSE |
| New Generation of Reactive Pre-Clean Prior to Barrier Seed Deposition to Preserve ULK Integrity | D. Galpin, STMicroelectronics |
| Alkoxysilane layers compat ibl with Cu deposit ion: towards new diffusion barriers? | P.H. Haumesser, CEA LETI MINATEC |
| Effect of Impurities and Microstructure of Cu Electroplating Films on Cu Interconnects Reliability Using CuAl Alloy Seed | S.Muranaka, Renesas |
| Electrical evaluation of PVD RuTa(N), RuW(N) and RuMn films as Cu diffusion barriers | H. Wojcik, Institute for Semiconductors and Microsystems |
Session 5: High-K Metal Gate & Contact | |
| The Role Of Metal \ High-K Dielectric Interfaces In Advanced Gate Stacks | M. Eizenberg, Technion |
| Process Development of High-k Metal Gate Aluminum CMP at 28nm Technology Node | Y. H. Hsieh, UMC |
| Scaling Tungsten Contact Metal Formation for 28nm CMOS Logic Fabrication | Y. Chen, UMC |
| Improved barrier properties of Ru/TaSiN stack on NiSi/Si for copper contact technology | X. P. Qu, Fudan University |
| Investigation of PVD TiN Process for 28nm Hi-K PMOS Effective Work Function Enhancement | Y. Chen, UMC |
Session 6: Emerging Technologies | |
| All-solid-state batteries: A challenging route towards 3D-integrated | P. Notten, Eindhoven University of Technology |
| Copper nanopart icles generated in situ in imidazolium based ionic liquids | P.H. Haumesser, CEA LETI MINATEC |
| Digitally Controllable RF Mems Inductor | A. Shirane, Tokyo Institute of Technology |
Poster Session | |
| Comparative Study of CVD TiN vs. ALD TiN for Contact Metallization in 32nm Node and Beyond | V. Arunachalam, GlobalFoundries |
| A Novel ChipA Chip--toto--Wafer (C2W) 3D Integration Approach using a Template for Precise AlignmentWafer Alignment | Q. Chen, RPI |
| Development of low-k precursors for next generation IC manufacturing | F. Doniat, Air Liquide |
| Chemical vapor deposition of ruthenium-phosphorus alloy films for Cu interconnect applications: Impact of the phosphorus source | J. Ekerdt, University of Texas |
| Highly corrosion resistant bright silver metallization deposited from a neutral cyanide-free solution | N. Fishelson, Tel Aviv University |
| Resistivity monitoring of the early stages of W CVD nucleation for sub-45 nm process | S. Haimson, Micron Israel Ltd |
| Effect of Low Electron Barrier Height Elements Addition on Nickel Silicide Contact Resistance for Advanced CMOS | H. C. Hsu, TSMC |
| NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive | J. Lai, UMC |
| Performance Improvement of Cu Dual-Damascene Interconnects by Seed Layer Enhancement | C. F. Lin, TSMC |
| Impact Of Increased Resistive Losses Of Metal Interconnects Upon ULSI Devices Reliability And Functionality | P. Livshits, Bar Ilan University |
| ULSI Silver And Copper Interconnect Microstructure Based Image Enhancement Algorithim | P. Livshits, Bar Ilan University |
| Silicon Precursor Development for Advanced Barriers | A. Mallikarjunan, Air Products and Chemicals, Inc. |
| Spacer Based Double Patterning Challenges and Solutions for 14nm node Logic Applications | B. Mebarki, Applied Materials |
| TiN/Titanium-Aluminum Oxynitride/Si as New Gate Structure for 3D Mos Technology | J. Miyoshi, University of Campinas |
| Low resistivity tungsten for 32 nm technology node MOL contacts and beyond | F. Papadatos, IBM |
| Titanium nitride as electrode for MOS Technology and Schottky Diode | L. Lima, University of Campinas |
| Development of Electrochemical Copper Deposition Screening Methodologies for Next Generation Additive Selection | K. Ryan, CNSE |
| Electromigration of Cu Iinterconnects Under AC and DC Test Conditions | R. Shaviv, Novellus |
| Isobutyl Silane Precursors for SiCH low-k Cap Layer Beyond the 22nm Node: Analysis of Film Structure for Compatability of Lower K-value and High Barrier Properties | H. Shimizu, Taiyo-Nippon Sanso Corporation |
| A Comparative Study of the Performance and Power Consumption of VLSI Circuits Based on Cu RIE and Cu Damascene Interconnect Technologies | S. Yuan, University of Tennessee |